MicroLogix HSC status bits

To view the current value of the HSC status bits, click on the HSC instruction and then select Display Special from the right mouse menu.

The control word for the MicroLogix 1000 high-speed counter instructions (C5:0) includes 15 status bits. HSC status bits are retentive. When the HSC is first configured, bits 3-7, 14, and 15 are reset and bit 1 is set.

Bit #	Status	Description
15	CU (Counter Up Enable)	(Used with all HSC counters) If 1 the HSC instruction is true. If 0 the HSC instruction is false. (Do not write to this bit.)
14	CD (Counter Down Enable)	(Used with Bidirectional counters) If 1 the HSC instruction is true. If 0 the HSC instruction is false. (Do not write to this bit.)
13	DN (High Preset Reached)	(An edge triggered latch bit when used with Up counters) If 1 the high preset was reached. Reset this bit with an OTU instruction or by executing an RAC or RES. (Reserved when used with Bidirectional counters)
12	OV (Overflow Occurred)	(With Up counters) If 1 the high preset is reached and DN bit is set. (With Bidirectional counters) If 1 the hardware accumulator transitioned from 32767 to -32768. You can reset this bit with an OTU instruction or by executing an RAC or RES instruction for both the up and bidirectional counter.
11	UN (Underflow Occurred)	(With Up counters this bit is reserved. Do not write to this bit.) (With Bidirectional counters) If 1 the hardware accumulator transitioned from 32767 to -32768. You can reset this bit with an OTU instruction or by executing an RAC or RES instruction.
10	UA (Update HSC Accumulator)	(Used with an OTE instruction) If 1 the OTE is enabled to update the instruction image accumulator value with the hardware accumulator value. The HSC instruction also performs this operation each time it is evaluated as true or false.
9	HP (Accumulator = High Preset)	(With Up counters this bit is reserved. Do not write to this bit.) (With Bidirectional counters) If 1 the hardware accumulator is greater than or equal to the high preset. If 0 the hardware accumulator is less than the high preset.
8	LP (Accumulator = Low Preset)	(With Up counters this bit is reserved. Do not write to this bit.) (With Bidirectional counters) If 1 the hardware accumulator is less than or equal to the low preset. If 0 the hardware accumulator is greater than the low preset.
7	IV (Overflow caused interrupt)	If 1 the HSC interrupt routine is being executed because of an overflow condition. When this bit is set the controller resets the IN, IH, and IL bits Examine this bit at the start of the HSC interrupt to determine why the interrupt occurred.
6	IN (Underflow caused interrupt)	If 1 the HSC interrupt routine is being executed because of an underflow condition. When this bit is set the controller resets the IV, IL, and IH bits. Examine this bit at the start of the HSC interrupt to determine why the interrupt occurred.
5	IH (High Preset reached caused interrupt)	If 1 the HSC interrupt routine is being executed because the high preset was reached. When this bit is set the controller resets the IV, IN, and IL bits. Examine this bit at the start of the HSC interrupt to determine why the interrupt occurred.
4	IL (Low Preset reached caused interrupt)	If 1 the HSC interrupt routine is being executed because the low preset was reached. When this bit is set the controller resets the IV, IN, and IH bits. Examine this bit at the start of the HSC interrupt to determine why the interrupt occurred.
3	PE (HSC Interrupt Pending)	If 1 the HSC interrupt is waiting for execution. The controller clears this bit when the HSC interrupt begins executing. An RAC or RES instruction also resets this bit. (Do not write to this bit.)
2	LS (HSC Interrupt Lost)	If 1 the HSC interrupt occurred while an interrupt was waiting for execution. Reset this bit with an OTU instruction or by executing an RAC or RES.
1	IE (HSC Interrupt Enable)	If 1 the HSC interrupt was enabled to run when an interrupt occurred or the HSC was just configured. If 0 the interrupt is disabled. (Do not write to this bit.)
0	(not used)