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Encoder (MicroLogix HSC)
The bidirectional counter (encoder) uses external inputs 0 and 1.
I:0/0 = Input A (turning On counts up)
I:0/1 = Input B (turning Off counts down)
The HSC instruction is executed true on the rising edge.
With this counter both high and low presets are used. The low preset value must be less than the high preset value or an error occurs. The high preset must be greater than the low preset or an error occurs.
Bidirectional counters operate in the -32768 to +32767 range inclusive and can be reset to zero using the Reset (RES) instruction.
After the first true HSC instruction execution, data can only be transferred to the hardware accumulator via a RES or RAC instruction, or to the hardware high and low presets via the HSL instruction.
Operation
When a high preset is reached:
- HP bit is set.
- HSC interrupt file (File 4) is executed if the interrupt is enabled.
- The IH bit is set and the IL, IV, and IN bits are reset.
When a low preset is reached:
- LP bit is set.
- HSC interrupt file (File 4) is executed if the interrupt is enabled.
- The IL bit is set and the IH, IV, and IN bits are reset.
An overflow occurs when the hardware accumulator transitions from +32767 to -32768. When this occurs:
- OV bit is set.
- HSC interrupt file (File 4) is executed if the interrupt is enabled.
- The IV bit is set and the IH, IL, and IN bits are reset.
- An underflow occurs when the hardware accumulator transitions from -32768 to +32767.
An underflow occurs when the hardware accumulator transitions from -32768 to +32767. When this occurs:
- UN bit is set.
- HSC interrupt file (File 4) is executed if the interrupt is enabled.
- The IN bit is set and the IH, IL, and IV bits are reset.